A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants

This article presents a fully on-chip low-power LDO voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating load current and provides fast load regulation achieved by applying a time-domain design methodology. Moreover, a new compensation technique is proposed and implemented to improve PSRR beyond the performance levels which can be obtained using the standard cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175 V/A, a line regulation of 0.024%, and a PSRR of 37 dB at 1MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8 V) within 1.6μs, at full load transition. The total ground current including the bandgap reference circuit is 28μA and the active chip area measures 290μm×360μm in a 0.18μm CMOS technolog

A Micropower Neural Recording Amplifier with Improved Noise Efficiency Factor

This article presents a neural recording amplifier suitable for large-scale integration with multi-electrode arrays (MEAs) in very low-power microelectronic cortical implants. The proposed amplifier is the most energy-efficient structure reported to date, which achieves an effective noise efficiency factor (NEF) smaller than the theoretical limit that was claimed in literature for any existing amplifier (NEF=2.02). The proposed technique, which is referred to as partially OTA sharing technique, achieves a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of systematic mismatch on crosstalk between adjacent channels and the trade-off between noise and crosstalk are theoretically analyzed. For an array of four neural amplifiers, simulation results show a midband gain of 39.2 dB and a -3dB bandwidth from 10 Hz to 10.6 kHz. The input referred noise is simulated to be 2.21 μVrms and the power consumption is 7.92 μW from 1.8 V supply, which refers to NEF=1.8. The worst-case crosstalk within the desired bandwidth is -46.1dB

A 16-channel 220 µW neural recording IC with embedded delta compression

A 16-channel neural action potential recording IC suitable for large-scale integration with multi-electrode arrays (MEAs) is presented. A closed-loop gain of 60 dB in the action potential band is achieved by cascading differential gain-stages utilizing a novel CMFB circuit. An oversampling delta modulator (DM) is proposed to improve the noise efficiency factor (NEF) of the recording system. Moreover, in-site compression is achieved by converting the derivative of the neural signal. The DM employs a novel dynamic voltage comparator with a partial reset preamplifier, which enhances the mean time to failure of the modulator. The proposed architecture is fabricated in a 0.18 μm CMOS technology. The total power consumption for 16 channels is 220 μW from a 1.2 V power supply. The SNDR is measured at 28.3 dB and 35.9 dB at the modulator and demodulator outputs, respectively. The total integrated in-band input-referred noise including the quantization noise of the ADC is measured at 2.8 μVrms, which corresponds to NEF=4.6 for the entire system

Human Tissue Plasminogen Activator Expression in Escherichia coli using Cytoplasmic and Periplasmic Cumulative Power

Abstract Tissue plasminogen activator (tPA) is a serine protease, which is composed of five distinct structural domains with 17 disulfide bonds, representing a model of high-disulfide proteins in human body. One of the most important limitations for high yield heterologous protein production in Escherichia coli (E. coli) is the expression of complex proteins with multiple disulfide bridges. In this study the combination of two distinct strategies, manipulated cytoplasm and native periplasm, was applied to produce the functional full length tPA enzyme in E. coli. Using a PelB signal peptide sequence at 5' site of tPA gene, the expression cassette was prepared and subsequently was transformed into a strain with manipulated oxidizing cytoplasm. Then the induction was made to express the protein of interest. The SDS-PAGE analysis and gelatin hydrolysis confirmed the successful expression of functional tPA. The results of this study showed that complex proteins can be produced in E. coli using the cumulative power of both cytoplasm and periplasm

Low-Power Circuits and Systems Design for Data Acquisition and Transmission in a Wireless Cortical Implant

Minimally invasive monitoring of the electrical activity of specific cortical areas using implantable microsystems offers the promise of diagnosing neurological diseases, as well as detecting and identifying neural activity patterns which are specific to a behavioral phenomenon. Multi-channel recording in-vivo impose critical constraints on circuits and systems design in order to comply with severe safety requirements. The system power consumption should be sufficiently small in order to enable autonomous and battery-less operation as well as to limit the temperature increase due to operation of the implant. Moreover, small area and volume of the implant are critical constraints to minimize issues associated with surgery operation and implantation. In this research, low-power circuits and systems techniques for data acquisition and transmission in wireless multi-channel cortical implants are presented. Wireless power transmission is carried out using an inductive coupling technique along with fully on-chip low-drop-out (LDO) voltage regulation. Stable operation over a wide range of load conditions, and fast load and line regulation are the main design issues of LDO regulators, which are addressed by proposing a novel compensation methodology, and a power supply rejection ratio (PSRR) boosting technique. Low-noise operation of the analog front-end is obtained by introducing new design techniques at circuit and system levels. The partial OTA sharing technique is proposed as a circuit-level approach which results in a significant reduction of power dissipation as well as silicon area, in addition to a very low noise efficiency factor (NEF). The effect of mismatch on crosstalk between channels, trade-off between noise and crosstalk, and nonlinearity of the amplifiers are theoretically analyzed and confirmed by measurement results. Three different system architectures are presented, which preserve the temporal information of the recording sites by avoiding channel multiplexing. A 16-channel neural recording system is presented, which uses an oversampling delta modulator as a dedicated ADC per channel. The oversampling delta modulator not only improves the system level NEF, but also provides in-site compression of the slow varying neural signal. The fabricated prototype consumes 220 μW from a 1.2 V power supply and achieves an input-referred noise equal to 2.8 μVrms. The application of algebraic Walsh-Hadamard coding in multi-channel recording systems is investigated by developing a 16-channel prototype. The linear and orthogonal combination of channels provided by coding, maps the spacial information of the channels to the temporal information of a superposed signal, and enables parallel recording from multiple channels using a single ADC. Moreover, this technique improves the spacial resolution of the recording sites by moving the shared signal processing hardware to the outside of the sensor plane. A fabricated chip supports a sensor pitch equal to 250 μm, consumes 359 μW from a 1.2 V power supply, and achieves an input-referred noise equal 4.1 μVrms. Finally, a system on a package (SoP) is presented which consists of a 64-channel neural recording system named Neuro+II, and an impulse radio ultra wideband (IR-UWB) transmitter. Neuro+II hosts the power conversion and voltage regulation blocks, the analog/mixed-mode front-end unit, and the digital baseband processing module. A dynamic power scaling technique is presented which enables 20.4% reduction in power consumtion of the analog/mixed-mode front-end. Neuro+II consumes 3.26 mW and achieves a power dissipation density equal to 13 mW/cm2. An IR-UWB transmitter is presented as an up-link communication module of the Neuro+II. An eight pulse-position modulation (8-PPM) scheme is implemented using a novel all-digital delayed-locked-loop (DLL) circuit, which offers better spectral compliance with USA Federal Communication Commision (FCC) regulations. A symmetric pulse combining technique is proposed to reduce the number of power amplifier elements by half, which enhances the tuning range capability of the transmitter. The fabricated transmiter consumes 540 μW and achieves an energy efficiency of 45 pJ/bit with an output power measured at -26 dBm. Continuous improvements in the field not only support research in the life science do- main, but also enables the clinical treatment of some diseases and extends the application field of such systems from clinical experiments to in-house treatments and ambulatory monitoring

Wireless cortical implantable systems

Wireless Cortical Implantable Systems examines the design for data acquisition and transmission in cortical implants. The first part of the book covers existing system-level cortical implants, as well as future devices. The authors discuss the major constraints in terms of microelectronic integration. The second part of the book focuses on system-level as well as circuit and system level solutions to the development of ultra low-power and low-noise microelectronics for cortical implants. Existing solutions are presented and novel methods and solutions proposed. The third part of the book focuses on the usage of digital impulse radio ultra wide-band transmission as an efficient method to transmit cortically neural recorded data at high data-rate to the outside world. Original architectural and circuit and system solutions are discussed

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 uVrms and the power consumption is 7.92 uW from a 1.8-V supply, which corresponds to NEF=3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are -43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256ux256u in 0.18 um complementary metal–oxide semiconductor technology

Low distortion switched-capacitor event-driven analog to digital converter

An event-driven tracking analog to digital converter (ADC) architecture is proposed. The proposed architecture has less sensitivity to amplifier and DAC non-linearity, reduces the swing and dynamic common-mode range requirement of the operational transconductance amplifier (OTA) and comparators, respectively